This invention relates generally to circuit boards holding programmable devices such as field programmable gate arrays, and specifically to methods for conserving surface area thereon.
FIG. 1 shows a conventional Field Programmable Gate Array (FPGA) 1 having an array of configurable logic blocks (CLBs) 2 surrounded by input/output blocks (IOBs) 3. The CLBs 2 are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure 4 includes a matrix of programmable switches (PSMs) 5 which can be programmed to selectively route signals between the various CLBs 2 and IOBs 3 and thus produce more complex functions of many input signals. The IOBs 3 can be configured to drive output signals from the CLBs 2 to external pins (not shown) of FPGA 1 and/or to receive input signals from the external FPGA pins.
The CLBs 2, IOBs 3, and PSMs 5 of FPGA 1 are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs 2, IOBs 3, and PSMs 5. These memory cells control various switches and multiplexers within respective CLBs 2, IOBs 3, and PSMs 5 which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA 1 via a configuration port 6 and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. Nos. Re34,363, 5,430,687, 5,742,531, and 5,844,829). Configuration port 6 is connected to the dedicated configuration structure by a configuration access port (CAP) 7, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in xe2x80x9cThe Programmable Logic Data Book 1998xe2x80x9d , published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG. 2. Well known design tool software operating on a suitable microprocessor within host system 20 creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system 20 to interface cable 15 using, for instance, a serial port or a USB port. The interface cable 15 preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system 20 into a format usable by target FPGA 10, although in some embodiments host system 20""s microprocessor is used to customize the configuration bitstream for target FPGA 10. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
In the past, the default configuration design for the on-board FPGA of interface cable 15 is stored in a dedicated non-volatile serial memory such as, for instance, a serial programmable read-only memory (SPROM). Upon power-up of interface cable 15, the FPGA configuration is read from the SPROM and provided to the FPGA, which configures itself accordingly.
As semiconductor processing technology advances, integrated circuits greatly increase in complexity and density. As the number of CLBs, IOBs, and PSMs within the on-board FPGA increases, so does the size of its configuration design. Similarly, as users desire increasing functionality, it is desirable to include more processing ability in the cable. A microcontroller is desirable. However, microcontrollers are typically booted up using microcode transmitted in parallel bytes from a device such as an SRAM or EEPROM or flash memory. As the size of devices to be tested increases, the size of the firmware code for a microcontroller increases. Accordingly, it is desirable to reduce the number of memory elements required to store the on-board FPGA configuration design and the microcontroller firmware code. Typical microcontrollers can not accept serial data one bit wide such as provided from the SPROM. If microcontroller firmware code is to be stored in an SPROM along with FPGA configuration data, the data format of the microcontroller firmware code must be changed before the data can be loaded into the microcontroller.
The present invention advantageously conserves board space by storing both the microcontroller firmware code and the on-board FPGA configuration data in the same memory. In accordance with the present invention, an FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device""s on-board FPGA and the firmware code for the interface device""s microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configuring itself, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code. Since both the on-board FPGA configuration design and the microcontroller firmware code are stored in a single memory, the dedicated parallel memory previously used to store the microcontroller firmware code may be eliminated, thereby advantageously conserving printed circuit board area.